Journal of Low Power Electronics and Applications - oalib

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Journal of Low Power Electronics and Applications

ISSN Print: 2079-9268

ISSN Online:

主页: http://www.mdpi.com/journal/jlpea

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Acknowledgement to Reviewers of the Journal of Low Power Electronics and Applications in 2014

Journal of Low Power Electronics Applications Editorial Office

Acknowledgement to Reviewers of the Journal of Low Power Electronics and Applications in 2014

Journal of Low Power Electronics Applications Editorial Office

Analog Encoding Voltage—A Key to Ultra-Wide Dynamic Range and Low Power CMOS Image Sensor

Arthur Spivak,Alexander Belenky,Alexander Fish,Orly Yadid-Pecht

Fully Integrated Solar Energy Harvester and Sensor Interface Circuits for Energy-Efficient Wireless Sensing Applications

Naser Khosro Pour,Fran？ois Krummenacher,Maher Kayal

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Pascal Meinerzhagen,Adam Teman,Robert Giterman,Andreas Burg,Alexander Fish

Designing Control Loops for Linear and Switching Power Supplies: A Tutorial Guide. By Christophe Basso, Artech House, 2012; 593 Pages. Price ￡99.00, ISBN 978-1-60807-557-7

Shu-Kun Lin

Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead Secure IC Design Methodology

Michael Linder,Jia Di,Scott C. Smith

Hardware Implementation of an Automatic Rendering Tone Mapping Algorithm for a Wide Dynamic Range Display

Chika Ofili,Stanislav Glozman,Orly Yadid-Pecht

Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits

Samer Houri,Christophe Poulain,Alexandre Valentian,Hervé Fanet

Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT) Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT) in a Digital Radio Mondiale (DRM) and DRM+ Receiver

Shin-Chi Lai,Yueh-Shu Lee,Sheau-Fang Lei

Synergistic Sensory Platform: Robotic Nurse

Igor Peshko,Romuald Pawluczyk,Dale Wick

Reconfigurable Threshold Logic Gates using Memristive Devices

Adrian Rothenbuhler,Thanh Tran,Elisa H. Barney Smith,Vishal Saxena,Kristy A. Campbell

A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers

Peter Beshay,Joseph F. Ryan,Benton H. Calhoun

Bias-Flip Technique for Frequency Tuning of Piezo-Electric Energy Harvesting Devices

Jianying Zhao,Yogesh Ramadass,Jeffrey Lang,Jianguo Ma,Dennis Buss

A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications

Aatmesh Shrivastava,Benton H. Calhoun

Sub-Threshold Standard Cell Sizing Methodology and Library Comparison

Bo Liu,Jose Pineda de Gyvez,Maryam Ashouei

Exploration of Charge Recycling DC-DC Conversion Using a Switched Capacitor Regulator

Kaushik Mazumdar,Mircea R. Stan

Low Power Dendritic Computation for Wordspotting

Suma George,Jennifer Hasler,Scott Koziol,Stephen Nease,Shubha Ramakrishnan

A Low Power CMOS Imaging System with Smart Image Capture and Adaptive Complexity 2D-DCT Calculation

Qing Gao,Orly Yadid-Pecht

Low-Gain, Low-Noise Integrated Neuronal Amplifier for Implantable Artifact-Reduction Recording System

Adeline Zbrzeski,No？lle Lewis,Francois Rummens,Ranu Jung,Gilles N'Kaoua,Abdelhamid Benazzouz,Sylvie Renaud

Short-Circuit Power Reduction by Using High-Threshold Transistors

Arkadiy Morgenshtein

CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors

Kushal Datta,Arindam Mukherjee,Guangyi Cao,Rohith Tenneti,Vinay Vijendra Kumar Lakshmi,Arun Ravindran,Bharat S. Joshi

Multi-Functional Micro Projection Device as Screen Substitute for Low Power Consumption Computing

Yuval Kapellner,Zeev Zalevsky

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Eitan N. Shauly

Analysis of Dynamic Differential Swing Limited Logic for Low-Power Secure Applications

Dina Kamel,Mathieu Renauld,David Bol,Fran？ois-Xavier Standaert,Denis Flandre

VLSI Architecture for 8-Point AI-based Arai DCT having Low Area-Time Complexity and Power at Improved Accuracy

Amila Edirisuriya,Arjuna Madanayake,Vassil S. Dimitrov,Renato J. Cintra,Jithra Adikari

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

James Boley,Jiajing Wang,Benton H. Calhoun

Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

Chien-Yu Lu,Ching-Te Chuang

Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation. J. Low Power Electron. Appl. 2012, 2, 168-179

Ameet Chavan,Praveen Palakurthi,Eric MacDonald,Joseph Neff,Eric Bozeman

A Multi-Channel Low-Power System-on-Chip for in Vivo Recording and Wireless Transmission of Neural Spikes

Andrea Bonfanti,Maria Ceravolo,Guido Zambra,Riccardo Gusmeroli,Gytis Baranauskas,Gian Nicola Angotzi,Alessandro Vato,Emma Maggiolini,Marianna Semprini,Alessandro Sottocornola Spinelli,Andrea Leonardo Lacaita

0.5 μW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 μm Fully Depleted Silicon-on-Insulator (FDSOI) Process

Piotr Olejarz,Kyoungchul Park,Samuel MacNaughton,Mehmet R. Dokmeci,Sameer Sonkusale

Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

Jani M？kip？？,Matthew J. Turnquist,Erkka Laulainen,Lauri Koskinen

Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation

Ameet Chavan,Praveen Palakurthi,Eric MacDonald,Joseph Neff,Eric Bozeman

Power Scalable Radio Receiver Design Based on Signal and Interference Condition

Satyam Dwivedi,Bharadwaj Amrutur,Navakanta Bhat

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

Sakkarapani Balagopal,Vishal Saxena

The Art of Directly Interfacing Sensors to Microcontrollers

Ferran Reverter

Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

David Bol

A Review and Modern Approach to LC Ladder Synthesis

Alexander J. Casson,Esther Rodriguez-Villegas

Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design

Ching-Hwa Cheng

Adaptative Techniques to Reduce Power in Digital Circuits

Bharadwaj Amrutur,Nandish Mehta,Satyam Dwivedi,Ajit Gupte

Quartz Resonator Based, 0.12 μW, 32768 Hz Oscillator with ±100 ppm Frequency Accuracy

Oleg Nizhnik,Kohei Higuchi,Kazusuke Maenaka

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

Ramesh Vaddi,Rajendra P. Agarwal,Sudeb Dasgupta,Tony T. Kim

Low Power Clock Network Design

Inna Vaisband,Eby G. Friedman,Ran Ginosar,Avinoam Kolodny

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Joseph Crop,Evgeni Krimer,Nariman Moezzi-Madani,Robert Pawlowski,Thomas Ruggeri,Patrick Chiang,Mattan Erez

Energy Efficient Supply Boosted Comparator Design

Suat U. Ay

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Xijiang Lin

A Low-Power Hardware-Friendly Binary Decision Tree Classifier for Gas Identification

Qingzheng Li,Amine Bermak

A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM

Xiaoxiao Zhang,Sylvain Leomant,Ka Lai Lau,Amine Bermak

Power-Performance Tradeoffs in Wide Dynamic Range Image Sensors with Multiple Reset Approach

Arthur Spivak,Adam Teman,Alex Belenky,Orly Yadid-Pecht,Alexander Fish

Path Specific Register Design to Reduce Standby Power Consumption

Emre Salman,Qi Qi

©2008-2017 OALib, Inc | Public user content licensed CC-BY 4.0 unless otherwise specified. OALib ISSN Online: 2333-9721 OALib ISSN Print: 2333-9705